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Design Verification Engineer

Ref: 80988

  • Negotiable
  • 16 May 2024
  • Cork (Centre)
  • Contract

Design Verification Engineer

Daily Rate Contract – Mostly Remote in Ireland


About the Company

My client is a world leading wireless technology innovator. They have an immediate requirement for a Senior Design Verification Engineer to join their team. This is a great opportunity to join one of the most established and innovative companies in the industry.


About the Position
Do you thrive on tackling complex challenges and shaping the future of technology?

We're seeking a talented and passionate Verification Engineer to join our dynamic team and play a key role in bringing next-generation sensor-based applications to life.
In this exciting role, you'll leverage your expertise in industry-leading verification methodologies to ensure the seamless integration of innovative sensor technologies into various consumer electronics devices. From smartphones and wearables to virtual reality and beyond, your work will have a tangible impact on the user experience.


Key Responsibilities

  • Collaborate with architects, designers, and other engineers to meticulously verify the functionality of sensor sub-systems.

  • Utilize industry-standard tools and methodologies (UVM, Formal Verification) to craft robust testbenches and verification environments.

  • Develop and execute comprehensive test plans to guarantee the highest quality standards.

  • Analyze coverage data and partner with design teams to optimize verification effectiveness.

  • Leverage your strong analytical skills to debug complex issues and ensure flawless integration.

  • Automate workflows using Python scripting to enhance team efficiency.

  • Contribute to a collaborative and fast-paced environment by effectively communicating progress and findings.


Experience/Requirements

We're looking for someone who:

  • Holds a Bachelor's degree in Science, Engineering, or a related field.

  • Possesses 4+ years of experience in ASIC design verification, UVM-based functional verification, or similar roles.

  • Demonstrates expertise in UVM, System Verilog, and Perl/Python scripting.

  • Thrives in a dynamic team environment and excels at collaboration.

  • Possesses excellent written and verbal communication skills.


Bonus points for:

  • Experience with formal verification tools (Jasper, VC_Formal).

  • Knowledge of sensor data processing.

  • Familiarity with SystemC and Matlab.

  • Experience with gate-level simulation debugging and power extraction tools.


Remuneration Package

A generous daily rate in line with experience will be on offer to suitable candidates.

This role can be fully remote in Ireland.


Contact

Please contact Derek Smyth on 01 5927861 or email or simply click the apply button.

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