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Apply advanced verification methodologies, including UVM and Formal Verification techniques.
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Develop robust testbenches and reusable verification components such as UVCs and C models.
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Verify sensor algorithm RTL for high-quality ASIC tapeout.
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Collaborate with design and systems teams to develop comprehensive test plans.
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Integrate C models into UVM frameworks.
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Write SystemVerilog assertions and debug bit-accurate test vectors.
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Analyze coverage metrics and work with design teams to close coverage gaps.
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Develop and maintain automated regression frameworks.
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Diagnose and resolve issues in regression test failures.
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Support higher-level system integration including test planning and debug.
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Automate workflows using Python to improve team efficiency.
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Participate in project reviews and support software/debug teams as required.
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Contribute to technical documentation.
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Bachelor's degree (or higher) in Engineering, Computer Science, or a related field.
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6+ years of experience in ASIC verification, including UVM-based and functional verification.
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Proficient in SystemVerilog and scripting languages such as Perl and Python.
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Strong experience with constrained-random verification, coverage-driven methodology, and assertion-based verification (SVA).
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Hands-on experience with RTL simulation and industry-standard verification tools.
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Familiarity with formal verification tools (e.g., Jasper, VC Formal), SystemC, and Matlab is a plus.
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Experience with gate-level simulation and power-aware verification tools is beneficial.
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Good understanding of C/C++.
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Excellent analytical and debugging skills.
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Strong written and verbal communication skills.
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Team-oriented with strong interpersonal capabilities.